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Archive for the ‘ne555’ tag

NE555 as Monostable – Retriggerable

NE555

NE555 on breadboard

What remains of monostable configuration is the retriggerable mode.

To be concise, the retriggerable version simply gives you the possibility to extend the period of the ON time, that we saw in the previous post fixed by the external components; this is done just by giving a new trigger input while the output is still HIGH.

What happens?
From that input instant a new period starts, and if no other triggering inputs occur, the output signal will continue to stay high for that fixed period of time more.

Because we talked about the necessity to have an input impulse with a duration far quicker than the output one, we assume it as a rule.

Now we must concentrate on the core of the discussion: how to get the signal retriggered.
In other words where we must act to get success.


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Written by riccardo

September 8th, 2013 at 1:04 pm

Posted in Hardware

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NE555 as Monostable – Time ON

Monostable-Diagram-NR

Non-retriggerable

We’re talking again of the monostable configuration: the timing calculation is the matter.
First of that we’d do better to have a closer look at the timing aspects.

As clearly seen the couple resistor-capacitor in input to pin 6 fixes the amount of time during which the output is high.
The simple multiplication returns a time dimension, but it must be corrected by a factor (a constant) to be determined.

To do this please refer to the above image: again we have a temporal diagram with a hypothetical flow of signals involved, for a non-retriggerable monostable.
Now the time is the main matter: how to determine a correct value for the tON at output?


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Written by riccardo

August 23rd, 2013 at 4:13 pm

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NE555 as Monostable – How to

Monostable-Diagram-NR

Monostable Diagram

Let’s continue answering to the last question in previous post.
After the switch pressure, which we tie the trigger pin to ground with, we surely get the latching couple (S,R)=(1,0).

We asked for the next state: (1,1) or (0,1)?
It depends by us: first occurs if we keep the trigger pin to ground, otherwise the Set condition is set to zero just by releasing the switch.

It’s worthwhile to examine these two possibilities, to better understand the timing issues involved.
[Note that diagrams are not at the same scale: take a qualitative look]

Let’s begin with the (0,1): this means that we release the pressure quite immediately.
By referring to the picture above we have in a bottom-up order the triggering event (which sets S=1), the charging of capacitor (until 2/3 Vcc which sets R=1), and finally the output which is quite-stable (and it’s quite Vcc).
All this keeping in mind that the quick release of switch make S=0.

The result is obvious: output becomes high for an amount of time dictated by the charging time of capacitor through resistor(s).
After that it returns to the stable state, here the low one.

What happens by keeping the switch pressed?

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Written by riccardo

July 28th, 2013 at 3:09 pm

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NE555 as Monostable

MonoStable-Scheme

NE555 – MonoStable Scheme

What is a monostable?
And how can it relate to a timer IC?

As the word could suggest, it’s something able to keep just one thing firmly.
For the NE555, or generally for a device, it must be intended as a condition itself.

But we know the name of the condition in jargon: state.
We talked about this concept introducing the S-R latch behavior indeed.

Well… in few words a monostable configuration simply means that 555 can keep stable only one between High and Low state. And to be precise the complete statement is monostable multi-vibrator.
Maybe what it has to be said is that in this case the output value matches with the state of the IC; but generally speaking these two concepts must be taken separately.
For our purpose we just consider them interchangeable.

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Written by riccardo

July 14th, 2013 at 2:28 pm

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NE555 – A deeper look inside

NE555-Internal-Circuit

NE555 – Internal Circuit

We’re going a little bit deeper in explaining the NE555.

Don’t worry about it; nothing difficult will be treated in spite of the complicated picture beside, which could announce a tremendously technical post.

We’ll concentrate only on few points to explicate what written in the two previous posts about this IC, especially to see the underlying structure of the S-R latch.

Pins are clearly signed in the electrical scheme representation making easy to recognize them: to facilitate things, inputs 2 and 6 are on the middle-left, power on top-left and bottom-left, and output on the right.
Pin 5 which finally we’ll talk about is conveniently going from near 6-threshold to the first node of the triple 5kΩ voltage divider.

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Written by riccardo

July 7th, 2013 at 8:36 am

Posted in Hardware

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