What remains of monostable configuration is the retriggerable mode.
To be concise, the retriggerable version simply gives you the possibility to extend the period of the ON time, that we saw in the previous post fixed by the external components; this is done just by giving a new trigger input while the output is still HIGH.
From that input instant a new period starts, and if no other triggering inputs occur, the output signal will continue to stay high for that fixed period of time more.
Because we talked about the necessity to have an input impulse with a duration far quicker than the output one, we assume it as a rule.
Now we must concentrate on the core of the discussion: how to get the signal retriggered.
In other words where we must act to get success.
We're talking again of the monostable configuration: the timing calculation is the matter.
First of that we'd do better to have a closer look at the timing aspects.
As clearly seen the couple resistor-capacitor in input to pin 6 fixes the amount of time during which the output is high.
The simple multiplication returns a time dimension, but it must be corrected by a factor (a constant) to be determined.
To do this please refer to the above image: again we have a temporal diagram with a hypothetical flow of signals involved, for a non-retriggerable monostable.
Now the time is the main matter: how to determine a correct value for the tON at output?
Let's continue answering to the last question in previous post.
After the switch pressure, which we tie the trigger pin to ground with, we surely get the latching couple (S,R)=(1,0).
We asked for the next state: (1,1) or (0,1)?
It depends by us: first occurs if we keep the trigger pin to ground, otherwise the Set condition is set to zero just by releasing the switch.
It's worthwhile to examine these two possibilities, to better understand the timing issues involved.
[Note that diagrams are not at the same scale: take a qualitative look]
Let's begin with the (0,1): this means that we release the pressure quite immediately.
By referring to the picture above we have in a bottom-up order the triggering event (which sets S=1), the charging of capacitor (until 2/3 Vcc which sets R=1), and finally the output which is quite-stable (and it's quite Vcc).
All this keeping in mind that the quick release of switch make S=0.
The result is obvious: output becomes high for an amount of time dictated by the charging time of capacitor through resistor(s).
After that it returns to the stable state, here the low one.